2024年2月9日发(作者：)

元器件交易网 Preliminary

PLL502-13

192MHz – 400MHz Low Phase Noise PECL VCXO (12 – 25MHz Crystal)

FEATURES

• Low phase noise output for the 192MHz to

400MHz range (-115 dBc at 10kHz offset).

• PECL output.

• 12 to 25MHz crystal input.

• Integrated crystal load capacitor: no external

load capacitor required.

• Output Enable selector.

• Wide pull range (min. +/-190 ppm)

• 3.3V operation.

• Available in 16 Pin TSSOP or SOIC.

PIN CONFIGURATION

VDDVDDXINXOUTOEVINGND121615VDDGND_BUFCLKBARVDD_BUFCLKGND_BUFGNDGNDPLL 502-31211109DESCRIPTION

The PLL502-13 is a monolithic low jitter and low

phase noise (-115dBc/Hz @ 10kHz offset) VCXO IC

with PECL output, for 192MHz to 400MHz output

range. It allows the control of the output frequency

with an input voltage (VIN), using a low cost crystal.

The chip provides a pullable output at a frequency of

FXIN x 16. This makes the PLL502-13 ideal for a wide

range of applications.

GNDFOUT = FXIN x 16

OE (Pin 5)

0 (Default)

1

Output State

Output enabled

Tri-state

Pin 5: Logical states are defined at PECL DIAGRAM

ReferenceDividerVCODividerPhaseComparatorChargePumpLoopFilterVCOCLKBARCLKXINXOUTXTALOSCVARICAPOEVIN47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 7/15/02 Page 1

元器件交易网 Preliminary

PLL502-13

192MHz – 400MHz Low Phase Noise PECL VCXO (12 – 25MHz Crystal)

PIN DESCRIPTIONS

Name

VDD

XIN

XOUT

OE

VIN

GND

GND_BUF

CLK

VDD_BUF

CLKB

Number

1,2,16

3

4

5

6

7,8,9,10

11,15

12

13

14

Type

P

I

I

I

I

P

P

O

P

O

Crystal input pin.

Crystal output pin.

Output enable input pin. Disables (tri-state) output when low. Internal

pull-up enables output by default if pin is not connected to low.

Frequency control voltage input pin.

GND Power connectors.

GND connector for output buffers.

True clock output pin.

+3.3V Power supply connector for output buffers.

Complementary clock output pin.

Description

+3.3V Power supply connectors.

ELECTRICAL SPECIFICATIONS

1. Absolute Maximum Ratings

PARAMETERS

Supply Voltage

Input Voltage, dc

Output Voltage, dc

Storage Temperature

Ambient Operating Temperature*

Junction Temperature

Lead Temperature (soldering, 10s)

Input Static Discharge Voltage Protection

SYMBOL

VDD

VI

VO

TS

TA

TJ

MIN.

VSS-0.5

VSS-0.5

-65

-40

MAX.

7

VDD+0.5

VDD+0.5

150

85

125

260

2

UNITS

V

V

V

°C

°C

°C

°C

kV

Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the

device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other

conditions above the operational limits noted in this specification is not implied.

* Note: Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for INDUSTRIAL grade only.

47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 7/15/02 Page 2

元器件交易网 Preliminary

PLL502-13

192MHz – 400MHz Low Phase Noise PECL VCXO (12 – 25MHz Crystal)

2. Crystal Specifications

PARAMETERS

Crystal Resonator

Frequency

Crystal Loading Rating

Crystal Pullability

Recommended ESR

SYMBOL

FXIN

CL (xtal)

CONDITIONS

Parallel Fundamental

Mode

At VIN = 1.65V

MIN.

12

TYP.

9.5

MAX.

25

250

30

UNITS

MHz

pF

-

Ω

C0/C1

(xtal)

AT cut

RE

AT cut

Note: Crystal Loading rating: 9.5pF is the loading the crystal sees from the VCXO chip at VIN = 1.65V. It is assumed that the crystal will be at nominal

frequency at this load. If the crystal requires more load to be at nominal frequency, the additional load must be added externally. This however may

reduce the pull range.

3. Voltage Control Crystal Oscillator

PARAMETERS

VCXO Stabilization Time *

SYMBOL

TVCXOSTB

CONDITIONS

From power valid

MIN.

TYP.

10

MAX.

UNITS

ms

VCXO Tuning Range

CLK output pullability

Linearity

VCXO Tuning Characteristic

VCON pin input impedance

VCON modulation BW

FXIN

= 12 - 25MHz;

XTAL C0/C1 < 250

0V ≤ VCON ≤ 3.3V

0V ≤ VCON ≤ 3.3V, -3dB

380

±190

2000

25

5

115

10

ppm

ppm

%

ppm/V

kΩ

kHz

Note: Parameters denoted with an asterisk (*) represent nominal characterization data and are not production tested to any specific limits.

4. General Electrical Specifications

PARAMETERS

Supply Current, Dynamic

(with Loaded Outputs)

Operating Voltage

Output Clock Duty Cycle

Short Circuit Current

SYMBOL

IDD

VDD

CONDITIONS

PECL

@ Vdd – 1.3V (PECL)

MIN.

3.13

45

TYP.

50

±50

MAX.

80

3.47

55

UNITS

mA

V

%

mA

47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 7/15/02 Page 3

元器件交易网 Preliminary

PLL502-13

192MHz – 400MHz Low Phase Noise PECL VCXO (12 – 25MHz Crystal)

5. Jitter and Phase Noise specification

PARAMETERS

Period jitter RMS at 311MHz

Accumulated jitter RMS at

311MHz

Integrated jitter RMS at 311MHz

Phase Noise relative to carrier

Phase Noise relative to carrier

Phase Noise relative to carrier

Phase Noise relative to carrier

Phase Noise relative to carrier

Note: Phase Noise measured at VIN = 0V

CONDITIONS

With capacitive decoupling

between VDD and GND.

With capacitive decoupling

between VDD and GND. Over

10,000 cycles.

Integrated 12 kHz to 20 MHz

311MHz @10Hz offset

311MHz @100Hz offset

311MHz @1kHz offset

311MHz @10kHz offset

311MHz @100kHz offset

MIN.

TYP.

9

TBM

4

-60

-90

-111

-115

-110

MAX.

UNITS

ps

ps

ps

dBc/Hz

dBc/Hz

dBc/Hz

dBc/Hz

dBc/Hz

47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 7/15/02 Page 4

元器件交易网 Preliminary

PLL502-13

192MHz – 400MHz Low Phase Noise PECL VCXO (12 – 25MHz Crystal)

6. PECL Electrical Characteristics

PARAMETERS

Output High Voltage

Output Low Voltage

SYMBOL

VOH

VOL

CONDITIONS

RL

= 50 Ω to (VDD – 2V)

(see figure)

MIN.

VDD – 1.025

MAX.

VDD – 1.620

UNITS

V

V

7. PECL Switching Characteristics

PARAMETERS

Clock Rise Time

Clock Fall Time

PECL Levels Test CircuitOUTVDDOUTSYMBOL

tr

tf

CONDITIONS

@20/80% - PECL

@80/20% - PECL

MIN.

TYP.

0.6

0.5

MAX.

1.5

1.5

UNITS

ns

ns

PECL Output Skew50Ω2.0V50%50ΩOUTOUTtSKEWPECL Transistion Time WaveformOUT80%50%20%OUTtRtF47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 7/15/02 Page 5

元器件交易网 Preliminary

PLL502-13

192MHz – 400MHz Low Phase Noise PECL VCXO (12 – 25MHz Crystal)

PACKAGE INFORMATION

16 PIN Narrow SOIC, TSSOP ( mm )SOICSymbolAA1BCDEHLeMin.1.350.100.330.199.803.805.800.401.27 BSCMax.1.750.250.510.2510.004.006.201.270.45Min.-0.050.190.094.904.30TSSOPMax.1.200.150.300.205.104.506.40 BSC0.750.65 BSCCLA

ORDERING INFORMATION

For part ordering, please contact our Sales Department:

47745 Fremont Blvd., Fremont, CA 94538, USA

Tel: (510) 492-0990 Fax: (510) 492-0991

PART NUMBER

The order number for this device is a combination of the following:

Device number, Package type and Operating temperature range

PLL502-13 S C XX

PART NUMBER

REVISION CODE

(when applicable)

TEMPERATURATURE

C=COMMERCIAL

M=MILITARY

I=INDUSTRAL

PACKAGE TYPE

S=SOIC, O=TSSOP

PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information

furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said

information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product.

LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the

express written approval of the President of PhaseLink Corporation.

47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 7/15/02 Page 6